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EMC2303
Multiple RPM-Based PWM Fan Controller
PRODUCT FEATURES
General Description
The EMC2303 is an SMBus compliant fan controller with up to three independently controlled PWM fan drivers. Each fan driver is controlled by a programmable frequency PWM driver and Fan Speed Control algorithm that operates in either a closed loop fashion or as a directly PWM-controlled device. The closed loop Fan Speed Control algorithm (FSC) has the capability to detect aging fans and alert the system. It will likewise detect stalled or locked fans and trigger an interrupt. Additionally, the EMC2303 offers a clock output so that multiple devices may be chained and slaved to the same clock source for optimal performance in large distributed systems.
Datasheet
Features
Three Programmable Fan Control circuits (EMC2303)
-- -- -- -- -- -- -- 4-wire fan compatible High speed PWM (26 kHz) Low speed PWM (9.5Hz - 2240 Hz) Optional detection of aging fans Fan Spin Up Control and Ramp Rate Control Alert on Fan Stall Up to 3 Selectable Default Fan Speeds
Watchdog Timer RPM-based fan control algorithm
-- 0.5% accuracy from 500 RPM to 16k RPM (external crystal oscillator) -- 1% accuracy from 500 RPM to 16k RPM (internal clock)
SMBus 2.0 Compliant
-- Up to 6 selectable SMBus addresses -- SMBus Alert compatible
Applications
Servers Projectors Industrial and Networking Equipment Notebook Computers
CLK Pin can provide a clock source output Available in a 12-pin 4mm x 4mm QFN Lead-free RoHS Compliant package
Block Diagram
CLK
TACH1 TACH2 TACH3 Tach Measurement Tachometer Limit Registers SMBus Slave Protocol
ADDR_SEL SMCLK SMDATA ALERT#
PWM1 PWM2 PWM3 PWM Drivers
Fan Speed Control Algorithm Fan Speed Control Algorithm Fan Speed Control Algorithm
SMSC EMC2303
DATASHEET
Revision 1.1 (10-12-09)
Multiple RPM-Based PWM Fan Controller Datasheet
ORDER NUMBER:
ORDERING NUMBER EMC2303-1-KP-TR PACKAGE 12-pin QFN (Lead-free RoHS compliant) FEATURES Three RPM-based fan speed control algorithms
This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.1 (10-12-09)
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SMSC EMC2303
DATASHEET
Multiple RPM-Based PWM Fan Controller Datasheet
Table of Contents
Chapter 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 SMBus Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.5 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.6 SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.7 SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 13 13 13 13 14 14 14 14 15 15 15 15
3.2
Chapter 4 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 4.3 4.4 Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RPM-based Fan Speed Control Algorithm (FSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Programming the RPM-based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Stalled Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Aging Fan or Invalid Drive Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Pull Up Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 Internal Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Power Up Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.1 Power Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.2 Continuous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 18 19 19 19 20 20 20 20 21 21 22 22 23 23 24
4.5
4.6 4.7 4.8
Chapter 5 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 5.2 5.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Fan Status - 24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Fan Stall Status - 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Fan Spin Status - 26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
25 28 28 29 29 30 30
SMSC EMC2303
Revision 1.1 (10-12-09)
DATASHEET
Multiple RPM-Based PWM Fan Controller Datasheet
5.4 5.5
5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23
5.3.4 Fan Drive Fail Status - 27h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 PWM Polarity Config - 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 PWM Output Config - 2Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Divide Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Spin Up Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Max Step Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Minimum Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid TACH Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30 30 31 31 31 31 32 33 33 35 36 37 39 40 40 41 41 42 43 43 44 45 45
Chapter 6 Typical Operating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 7.2 EMC2303 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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SMSC EMC2303
DATASHEET
Multiple RPM-Based PWM Fan Controller Datasheet
List of Figures
Figure 1.1 Figure 3.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 EMC2303 Pin Diagram (12-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Diagram of EMC2303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package Drawing - 12-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Package Dimensions - 12-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PCB Footprint - 12-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EMC2303 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SMSC EMC2303
5
Revision 1.1 (10-12-09)
DATASHEET
Multiple RPM-Based PWM Fan Controller Datasheet
List of Tables
Table 1.1 Pin Description for EMC2303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.1 ADDR_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.2 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.4 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.5 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.6 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3.7 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3.8 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3.9 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.1 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4.2 CLK Pin Pull-Up Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5.1 EMC2303 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5.2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5.3 Fan Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5.4 Fan Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5.5 PWM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 5.6 PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 5.7 PWM_BASEx[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 5.8 Fan Driver Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 5.9 PWM Divide Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 5.10 Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 5.11 Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 5.12 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 5.13 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 5.14 Fan Configuration 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 5.15 Derivative Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5.16 Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5.17 Gain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5.18 Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 5.19 Fan Spin Up Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 5.20 DRIVE_FAIL_CNT[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 5.21 Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 5.22 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 5.23 Fan Max Step Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 5.24 Minimum Fan Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5.25 Valid TACH Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5.26 Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 5.27 TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 5.28 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 5.29 Software Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 5.30 Product Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 5.31 ADDR_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5.32 FAN_SPD Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5.33 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5.34 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 5.35 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Chapter 1 Pin Description
SMDATA 1 SMCLK 2 VDD 3
10 ALERT# 9 CLK 8 TACH2 7 PWM2
PIN FUNCTION
12 TACH3 4 ADDR_SEL
PIN NUMBER 1 2 3 4 PIN NAME SMDATA SMCLK VDD ADDR_SEL
EMC2303 12-QFN
5 PWM1
11 PWM3
Figure 1.1 EMC2303 Pin Diagram (12-Pin QFN)
Table 1.1 Pin Description for EMC2303 PIN TYPE DIOD (5V) DI (5V) Power AIO DO OD (5V)
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SMBus data input/output - requires external pull-up resistor SMBus clock input - requires external pull-up resistor Power Supply Address selection input - requires pull-up resistor Push-Pull PWM output driver for Fan 1
5
PWM1 Open Drain PWM output driver for Fan 1
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Table 1.1 Pin Description for EMC2303 (continued) PIN NUMBER 6 PIN NAME TACH1 PIN FUNCTION Open drain tachometer input for Fan 1requires pull-up resistor Push-Pull PWM output driver for Fan 2 7 PWM2 Open Drain PWM output driver for Fan 2 8 TACH2 Open drain tachometer input for Fan 2 requires pull-up resistor Clock input for tachometer measurement 9 CLK Push Pull Clock output to other fan controllers to cynchronize Fan Speed Control Active low interrupt - requires external pull-up resistor. Push-Pull PWM output driver for Fan 3 11 PWM3 Open Drain PWM output driver for Fan 3 12 Bottom Pad TACH3 GND Open drain tachometer input for Fan 3 requires pull-up resistor Ground OD (5V) DI (5V) Power OD (5V) DI (5V) DI (5V) DO PIN TYPE DI (5V) DO
10
ALERT#
OD (5V) DO
The pin types are described in detail below. All pins labeled with (5V) are 5V tolerant. APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the voltage difference between VDD and the 5V tolerant pad must never be more than 3.6V.
Table 1.2 Pin Types PIN TYPE Power AIO DI DO DESCRIPTION This pin is used to supply power or ground to the device. Analog input / output - this pin is used for analog signals Digital Input - this pin is used as a digital input. This pin is 5V tolerant. Push / Pull Digital Output - this pin is used as a digital output. It can both source and sink current. Digital Input / Open Drain Output this pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. Open Drain Digital Output - this pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant.
DIOD
OD
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Chapter 2 Electrical Specifications
Table 2.1 Absolute Maximum Ratings Voltage on 5V tolerant pins (V5VT_pin) Voltage on 5V tolerant pins (|V5VT_pin - VDD|) (see Note 2.1) Voltage on VDD pin Voltage on any other pin to GND Package Thermal Resistance - Junction to Ambient (JA) Operating Ambient Temperature Range Storage Temperature Range ESD Rating, All Pins, HBM -0.3 to 5.5 0 to 3.6 -0.3 to 4 -0.3 to VDD + 0.3 50 -40 to 125 -55 to 150 2000 V V V V C/W C C V
Note: Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 2.1 For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the EMC2303 is unpowered.
2.1
Electrical Specifications
Table 2.2 Electrical Specifications VDD = 3V to 3.6V, TA = -40C to 125C, all Typical values at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP DC Power
MAX
UNIT
CONDITIONS
Supply Voltage Supply Current
VDD IDD
3
3.3 475
3.6 600
V uA
PWM Fan Driver PWM Resolution PWM Duty Cycle PWM DUTY 0 256 100 RPM-based Fan Controller Tachometer Range Tachometer Setting Accuracy Input High Voltage Input Low Voltage TACH 480 0.5 1 2.0 0.8 16000 1 2 RPM % % V V External oscillator 32.768kHz Internal Oscillator Steps %
TACH TACH
VIH VIL
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Table 2.2 Electrical Specifications (continued) VDD = 3V to 3.6V, TA = -40C to 125C, all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC Output High Voltage Output Low Voltage Leakage current ILEAK 5 uA SYMBOL VOH VOL MIN VDD 0.4 0.4 TYP MAX UNIT V V CONDITIONS 8 mA current drive 8 mA current sink ALERT# pin Powered and unpowered 0C < TA < 85C pull-up voltage < 3.6V
Note 2.2
All voltages are relative to ground.
2.2
SMBus Electrical Specifications
Table 2.3 SMBus Electrical Specifications VDD= 3V to 3.6V, TA = -40C to 125C Typical values are at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High/Low Current Input Capacitance VIH VIL VOH VOL IIH / IIL CIN 5 SMBus Timing Clock Frequency Spike Suppression Bus free time Start to Stop Setup Time: Start Setup Time: Stop Data Hold Time Data Setup Time fSMB tSP tBUF tSU:STA tSU:STP tHD:DAT tSU:DAT 1.3 0.6 0.6 0.6 0.6 6 72 10 400 50 kHz ns us us us us us VDD - 0.4 0.4 5 2.0 0.8 V V V V uA pF 4 mA current sink Powered and unpowered 0C < TA < 85C
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Table 2.3 SMBus Electrical Specifications (continued) VDD= 3V to 3.6V, TA = -40C to 125C Typical values are at TA = 27C unless otherwise noted. CHARACTERISTIC Clock Low Period Clock High Period Clock/Data Fall time Clock/Data Rise time Capacitive Load SYMBOL tLOW tHIGH tFALL tRISE CLOAD MIN 1.3 0.6 300 300 400 TYP MAX UNITS us us ns ns pF Min = 20+0.1CLOAD ns Min = 20+0.1CLOAD ns per bus line CONDITIONS
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Chapter 3 Communications
3.1 System Management Bus Interface Protocol
The EMC2303 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported; however, the EMC2303 will not stretch the clock signal.
TLOW
THIGH
THD:STA TSU:STO
SMCLK
THD:STA
TRISE
TFALL
THD:DAT
TSU:DAT
TSU:STA
SMDATA
TBUF
P
S
S - Start Condition
S
P - Stop Condition P
Figure 3.1 SMBus Timing Diagram
3.1.1
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic `1' state to a logic `0' state while the SMBus Clock line is in a logic `1' state.
3.1.2
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by a RD / WR indicator bit. If this RD / WR bit is a logic `0', then the SMBus Host is writing data to the client device. If this RD / WR bit is a logic `1', then the SMBus Host is reading data from the client device. The SMBus client will respond to one of multiple SMBus addresses determined by the pull-up resistor on the ADDR_SEL pin. The ADDR_SEL pin decodes one of six pull-up resistors upon device power up. Depending on the resistor used, the CLK pin may also be used to select additional functionality.
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Table 3.1 ADDR_SEL Pin Decode PULL-UP RESISTOR 4.7k Ohm 5% 6.8k Ohm 5% 10k Ohm 5% 15k Ohm 5% 22k Ohm 5% 33k Ohm 5% SMBUS ADDRESS 0101_110(r/w) 0101_111(r/w) 0101_100(r/w) 0101_101(r/w) 1001_100(r/w) 1001_101(r/w) CLK pin used to determine default fan drive - see Section 4.5.1. The CLK pin cannot be used as a clock input or output None - CLK pin used as clock input or output ADDITIONAL FUNCTIONS
3.1.3
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.1.4
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it matches and the ARA address if the ALERT# pin is asserted). This is done by the client device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. The Host will NACK (not acknowledge) the data received from the client by holding the SMBus data line high after the 8th data bit has been sent.
3.1.5
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic `0' state to a logic `1' state while the SMBus clock line is in a logic `1' state. When the EMC2303 detects an SMBus Stop bit has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications.
3.1.6
SMBus Time-out
The EMC2303 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus, the device will time-out and reset the SMBus interface. The SMBus timeout feature is disabled by default and can be enabled via clearing the DIS_TO bit in the Configuration register (20h).
3.1.7
SMBus and I2C Compliance
The major difference between SMBus and I2C devices is highlighted here. For complete compliance information refer to the SMBus 2.0 specification. 1. Minimum frequency for SMBus communications is 10kHz (I2C has no minimum frequency). 2. The slave protocol will reset if the clock is held low for longer than 30ms (I2C has no timeout). 3. The slave protocol will reset if both the clock and data lines are held high for longer than 150us. 4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
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5. The Block Read and Block Write protocols are only compliant with I2C data formatting. They do not support SMBus formatting for Block Read and Block Write protocols.
3.2
SMBus Protocols
The EMC2303 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte and Write Byte as valid protocols as shown below. It will respond to the Alert Response Address protocol but is not in full compliance. All of the below protocols use the convention in Table 3.2. When reading the protocol blocks, the value of YYYY_YYYb should be replaced with the respective SMBus addresses.
Table 3.2 Protocol Format DATA SENT TO DEVICE # of bits sent DATA SENT TO THE HOST # of bits sent
3.2.1
Write Byte
The Write Byte is used to write one byte of data to the registers as shown below Table 3.3.
Table 3.3 Write Byte Protocol SLAVE ADDRESS YYYY_YYYb REGISTER ADDRESS XXh REGISTER DATA XXh
START 1 -> 0
WR 0
ACK 0
ACK 0
ACK 0
STOP 0 -> 1
3.2.2
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 3.4.
Table 3.4 Read Byte Protocol
START SLAVE ADDRESS YYYY_YYYb WR ACK Register Address XXh ACK START Slave Address YYYY_YYYb RD ACK Register Data XXh NACK STOP
1 -> 0
0
0
0
0 -> 1
1
0
1
0 -> 1
3.2.3
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 3.5.
Table 3.5 Send Byte Protocol SLAVE ADDRESS YYYY_YYYb REGISTER ADDRESS XXh
START 1 -> 0
WR 0
ACK 0
ACK 0
STOP 0 -> 1
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3.2.4
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 3.6.
Table 3.6 Receive Byte Protocol SLAVE ADDRESS YYYY_YYYb
START 1 -> 0
RD 1
ACK 0
REGISTER DATA XXh
NACK 1
STOP 0 -> 1
3.2.5
Block Write Protocol
The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 3.7. It is an extension of the Write Byte Protocol.
Table 3.7 Block Write Protocol SLAVE ADDRESS YYYY_YYYb REGISTER ADDRESS XXh REGISTER DATA XXh
START 1 ->0 REGISTER DATA XXh
WR 0 REGISTER DATA XXh
ACK 0
ACK 0 REGISTER DATA XXh
ACK 0
ACK 0
ACK 0
... ...
ACK 0
STOP 0 -> 1
3.2.6
Block Read Protocol
The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 3.8. It is an extension of the Read Byte Protocol.
Table 3.8 Block Read Protocol
START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK START SLAVE ADDRESS RD ACK REGISTER DATA
1->0
ACK
YYYY_YYYb
REGISTER DATA
0
ACK
0
REGISTER DATA
XXh
ACK
0
REGISTER DATA
1 ->0
ACK
YYYY_YYYb
...
1
REGISTER DATA
0
NACK
XXh
STOP
0
XXh
0
XXh
0
XXh
0
...
XXh
1
0 -> 1
3.2.7
Alert Response Address
The ALERT# output can be used as a processor interrupt or as an SMBus Alert when configured to operate as an interrupt. When it detects that the ALERT# pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 0001_100xb. All devices with active interrupts will respond with their client address as shown in Table 3.9.
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Table 3.9 Alert Response Address Protocol ALERT RESPONSE ADDRESS 0001_100b
START 1 -> 0
RD 1
ACK 0
DEVICE ADDRESS YYYY_YYYb
NACK 1
STOP 0 -> 1
The EMC2303 will respond to the ARA in the following way if the ALERT# pin is asserted. 1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2. Set the MASK bit to clear the ALERT# pin.
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Chapter 4 Product Description
The EMC2303 is an SMBus compliant fan controller with three programmable frequency PWM fan drivers. The fan drivers can be operated using two modes: the RPM-based Fan Speed Control Algorithm or the direct fan drive setting. Figure 4.1 shows a system diagram of the EMC2303.
3.3V
VDD SMCLK TACH3 PWM3 ALERT# ADDR_SEL
tachometer
MCU
SMDATA
Drive Circuit
EMC2303
TACH2
tachometer
tachometer
TACH1 PWM1 GND
PWM2
Drive Circuit 32.768KHz Clock Input or Output
Drive Circuit
CLK
Figure 4.1 System Diagram of EMC2303
4.1
Fan Control Modes of Operation
The EMC2303 has two modes of operation for each fan driver. Each mode of operation uses the Ramp Rate control and Spin Up Routine. 1. Direct Setting Mode - in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver Setting Register (see Section 5.7) will instantly update the PWM fan drive. Ramp Rate control is optional and enabled via the EN_RRC bits. Whenever the Direct Setting Mode is enabled, the current drive will be changed to what was last written into the Fan Driver Setting Register. 2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a target tachometer count and the PWM drive setting is automatically updated to achieve this target speed. The algorithm uses the Spin Up Routine and has user definable ramp rate controls. This mode is enabled setting the EN_ALGO bit in the Fan Configuration Register.
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Table 4.1 Fan Controls Active for Operating Mode DIRECT SETTING MODE Fan Driver Setting (read / write) EDGES[1:0] UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Valid TACH Count TACH Reading FSC MODE Fan Driver Setting (read only) EDGES[1:0] (Fan Configuration) RANGE[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Fan Minimum Drive Valid TACH Count TACH Target (read / write) TACH Reading DRIVE_FAIL_CNT[1:0] and Drive Band Fail Registers
4.2
PWM Fan Driver
The EMC2303 supports 3 PWM output drivers. Each output driver can be configured to operate as an open-drain (default) or push-pull driver and each driver can be configured with normal or inverse polarity. Additionally, the PWM frequencies are independently programmable with ranges from 9.5Hz to 26kHz in four programmable frequency bands.
4.3
RPM-based Fan Speed Control Algorithm (FSC)
The EMC2303 includes 3 RPM-based Fan Speed Control Algorithms. Each algorithm operates independently and controls a separate fan driver. Each algorithm is controlled manually (by setting the target fan speed). This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach and maintain the system's desired fan speed to an accuracy directly proportional to the accuracy of the clock source. The desired tachometer count is set by the user inputting the desired number of 32.768kHz cycles that occur per fan revolution. This is done by manually setting the TACH Target Register. The user may change the target count at any time. The user may also set the target count to FFh in order to disable the fan driver for lower current operation. For example, if a desired RPM rate for a 2-pole fan is 3000 RPMs, then the user would input the hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs.
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The EMC2303's RPM-based Fan Speed Control Algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT# pin. The EMC2303 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The fan controller will function either with an externally supplied 32.768kHz clock source or with it's own internal 32kHz oscillator depending on the required accuracy. The EMC2303 offers a clock output that enables additional devices to be slaved to the same clock source.
4.3.1
Programming the RPM-based Fan Speed Control Algorithm
The RPM-based Fan Speed Control Algorithm is disabled upon device power up. The following registers control the algorithm. The EMC2303 fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. Note that steps 1 - 6 are optional and need only be performed if the default settings do not provide the desired fan response. 1. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired. 2. Set the Fan Step Register to the desired step size. 3. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation. 4. Set the Update Time and Edges options in the Fan Configuration Register. 5. Set the Valid TACH Count Register to the highest tach count that indicates the fan is spinning. Refer to AN17.4 RPM to TACH Counts Conversion for examples and tables for supported RPM ranges (500, 1k, 2k, 4k). 6. Set the TACH Target Register to the desired tachometer count. 7. Enable the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit.
4.4
Tachometer Measurement
The tachometer measurement circuitry is used in conjunction with the RPM-based Fan Speed Control Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a diagnostic for host based fan control. This method monitors the TACHx signal in real time. It constantly updates the tachometer measurement by reporting the number of clocks between a user programmed number of edges on the TACHx signal (see Table 5.12). The tachometer measurement provides fast response times for the RPM-based Fan Speed Control Algorithm and the data is presented as a count value that represents the fan RPM period.
APPLICATION NOTE: The tachometer measurement method works independently of the drive settings. If the device is put into Direct Setting and the fan drive is set at a level that is lower than the fan can operate (including zero drive), then the tachometer measurement may signal a Stalled Fan condition and assert an interrupt.
4.4.1
Stalled Fan
A Stalled fan is detected if the tach counter exceeds the user-programmable Valid TACH Count setting. If a stall is detected, the device will flag the fan as stalled and trigger an interrupt. If the RPM-based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled. The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the mode of operation.
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Whenever the Direct Setting Mode or the Spin Up Routine is enabled, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table 5.22) to allow the fan to reach a valid speed without generating unnecessary interrupts. In Direct Setting Mode, whenever the TACH Reading Register value exceeds the Valid TACH Count Register setting, the FAN_STALL status bit will be set. When using the RPM-based Fan Speed Control Algorithm, the stalled fan condition is checked whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.
4.4.2
Aging Fan or Invalid Drive Detection
This is useful to detect aging fan conditions (where the fan's natural maximum speed degrades over time) or a speed setting that is faster than the fan is capable of. The EMC2303 contains circuitry that detects that the programmed fan speed can be reached by the fan. If the target fan speed cannot be reached within a user defined band of tach counts at maximum drive, the DRIVE_FAIL status bits are set and the ALERT# pin is asserted.
4.5
CLK Pin
The CLK pin has multiple functionality as determined by the pull-up decode of the ADDR_SEL pin and the settings of the Configuration register. The functionality associated with the CLK pin upon device power up is independent of the CLK pin functionality after the device has been configured.
4.5.1
Pull Up Decode
If additional functionality is enabled via the ADDR_SEL pin (see Section 3.1.2), then the CLK pin should be configured with a pull-up resistor to VDD and should not be used. The value of the pull-up resistor on the CLK pin is used to determine the default drive state of all fan drivers as shown in Table 4.2.
Table 4.2 CLK Pin Pull-Up Decode PULL-UP RESISTOR 4.7k Ohm 5% 6.8k Ohm 5% 10k Ohm 5% 15k Ohm 5% 22k Ohm 5% 33k Ohm 5% FAN DEFAULT DRIVE SETTING 0% - OFF 30% 50% 75% 100% 0% - OFF
4.5.2
External Clock
The EMC2303 allows the user to choose between supplying an external 32.768kHz clock or use of the internal 32kHz oscillator to measure the tachometer signal. This clock source is used by the RPMbased Fan Speed Control Algorithm to calculate the current fan speed. This fan controller accuracy is directly proportional to the accuracy of the clock source. When this function is used, the external clock is driven into the device via the CLK pin.
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4.5.3
Internal Clock
Alternately, the EMC2303 may be configured to use its internal clock as a clock output to drive other fan driver devices. When configured to operate in this mode, the device uses its internal clock for tachometer reading and drives the CLK pin using a push-pull driver.
4.6
Spin Up Routine
The EMC2303 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. The Spin Up Routine is initiated in Direct Setting mode when the setting value changes from 00h to anything else. When the Fan Speed Control Algorithm is enabled, the Spin Up Routine is initiated under the following conditions: 1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid TACH Count (see Section 5.15). 2. The RPM-based Fan Speed Control Algorithm's measured TACH Reading Register value is greater than the Valid TACH Count setting. When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of the total user defined spin up time. For the remaining spin up time, the fan driver output is set at a user defined level (30% through 65% drive). After the Spin Up Routine has finished, the EMC2303 measures the TACHx signal. If the measured TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan. Figure 4.2 shows an example of the Spin Up Routine in response to a programmed fan speed change based on the first condition above.
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100% (optional)
30% through 65% Fan Step
New Target Count Algorithm controlled drive Prev Target Count = FFh 1/4 of Spin Up Time
Update Time Spin Up Time
Target Count Changed
Check TACH
Target Count Reached
Figure 4.2 Spin Up Routine
4.6.1
Power Up Options
The EMC2303 allows for one of four fan speed options upon device power up depending on the status of the pull-up resistor on the ADDR_SEL pin and the CLK pin. If the ADDR_SEL pin decode enables the CLK pin (see Table 3.1), then the value of the pull-up resistor on the CLK pin is used to determine the default fan drive setting (see Section 4.5.1). If the Fan drive setting is set at a non-zero value (as determined by the CLK pin), then the drive setting will be set to the desired setting. The Spin Up Routine will not be activated. This function does not disable the Watchdog timer which will continue to function normally. See Section 4.8.
4.7
Ramp Rate Control
The Fan Driver can be configured with automatic ramp rate control. Ramp rate control is accomplished by adjusting the drive output settings based on the Maximum Fan Step Register settings and the Update Time settings. If the RPM-based Fan Speed Control Algorithm is used, then this ramp rate control is automatically used. The user programs a maximum step size for the fan drive setting and an update time. The update time varies from 100ms to 1.6s while the fan drive maximum step can vary from 1 count to 31 counts. When a new fan drive setting is entered, the delta from the next fan drive setting and the previous fan drive setting is determined. If this delta is greater than the Max Step settings, then the fan drive setting is incrementally adjusted every 100ms to 1.6s as determined by the Update Time until the target fan drive setting is reached. See Figure 4.3.
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Next Desired Setting Max Step Max Step
Previous Setting
Update Time
Update Time
Setting Changed
Figure 4.3 Ramp Rate Control
4.8
Watchdog Timer
The EMC2303 contains an internal Watchdog Timer for all fan drivers. The Watchdog timer monitors the SMBus traffic for signs of activity and works in two different modes based upon device operation. These modes are Power Up Operation and Continuous Operation as described below. For either mode of operation, if four (4) seconds elapse without activity detected by the host, then the watchdog will be triggered and the following will occur: 1. The WATCH status bit will be set. 2. The fan driver will be set to full scale drive. It will remain at full scale drive until it is disabled.
APPLICATION NOTE: When the Watchdog timer is activated, the Fan Speed Control Algorithm is automatically disabled. Disabling the Watchdog will not automatically set the fan drive nor re-activate the Fan Speed Control Algorithm. This must be done manually.
4.8.1
Power Up Operation
The Watchdog Timer only starts immediately after power-up. Once it has been triggered or deactivated, it will not restart although it can be configured to operate in Continuous operation. While the Watchdog timer is active, the device will not check for a Stalled Fan condition. In the Power Up Operation, the Watchdog Timer is disabled by any of the following actions: 1. Writing the Fan Setting Register will disable the Watchdog Timer. 2. Enabling the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the Watchdog Timer. The fan driver will be set based on the RPM-based Fan Speed Control Algorithm. Writing any other configuration registers will not disable the Watchdog Timer upon power up.
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4.8.2
Continuous Operation
When configured to operate in Continuous Operation, the Watchdog timer will start immediately. The timer will be reset by any access (read or write) to the SMBus register set. The four second Watchdog timer will restart upon completion of SMBus activity.
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Chapter 5 Register Set
5.1 Register Map
The following registers are accessible through the SMBus Interface. All register bits marked as `-' will always read `0'. A write to these bits will have no effect.
Table 5.1 EMC2303 Register Set REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Configuration and control
LOCK
PAGE
20h 24h 25h 26h 27h 29h 2Ah 2Bh 2Dh
R/W R-C R-C R-C R-C R/W R/W R/W R/W
Configuration Fan Status Fan Stall Status Fan Spin Status Drive Fail Status Fan Interrupt Enable Register PWM Polarity Config PWM Output Config PWM Base Frequency
Configures the clocking and watchdog functionality Stores the status bits for the RPMbased Fan Speed Control Algorithm Stores status bits associated with a stalled fan Stores status bits associated with a spin-up failure Stores status bits associated with drive failure Controls the masking of interrupts on all fan related channels Configures Polarity of all PWM drivers Configures Output type of PWM drivers Selects the base frequency for PWM outputs 3 - 1 Fan 1 Control Registers Always displays the most recent fan driver input setting for Fan 1. If the RPM-based Fan Speed Control Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the frequency for Fan 1 Sets configuration values for the RPMbased Fan Speed Control Algorithm for the Fan 1 driver Sets additional configuration values for the Fan 1driver Holds the gain terms used by the RPMbased Fan Speed Control Algorithm for the Fan 1 driver
40h 00h 00h 00h 00h 00h 00h 00h 00h
SWL No No No No No No No No
Page 28 Page 29 Page 29 Page 29 Page 29 Page 30 Page 31 Page 31 Page 31
30h
R/W
Fan 1 Setting
00h
No
Page 32
31h
R/W
PWM 1 Divide Fan 1 Configuration 1 Fan 1 Configuration 2 Gain 1
01h
No
Page 33
32h
R/W
2Bh
No
Page 33
33h
R/W
28h
SWL
Page 35
35h
R/W
2Ah
SWL
Page 36
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Table 5.1 EMC2303 Register Set (continued) REGISTER NAME Fan 1 Spin Up Configuration Fan 1 Max Step Fan 1 Minimum Drive Fan 1 Valid TACH Count Fan 1 Drive Fail Band Low Byte Fan 1 Drive Fail Band High Byte TACH 1 Target Low Byte TACH 1 Target High Byte TACH 1 Reading High Byte TACH 1 Reading Low Byte DEFAULT VALUE 19h 10h 66h (40%) F5h 00h 00h F8h FFh FFh F8h
ADDR 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
FUNCTION Sets the configuration values for Spin Up Routine of the Fan 1driver Sets the maximum change per update for the Fan 1 driver Sets the minimum drive value for the Fan 1 driver Holds the tachometer reading that indicates Fan 1 is spinning properly Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive Holds the target tachometer reading low byte for Fan 1 Holds the target tachometer reading high byte for Fan 1 Holds the tachometer reading high byte for Fan 1 Holds the tachometer reading low byte for Fan 1 Fan 2 Control Registers Always displays the most recent fan driver input setting for Fan 2. If the RPM-based Fan Speed Control Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the frequency for Fan 2 Sets configuration values for the RPMbased Fan Speed Control Algorithm for Fan 2 Sets additional configuration values for the Fan 2 driver Holds the gain terms used by the RPMbased Fan Speed Control Algorithm for Fan 2 Sets the configuration values for Spin Up Routine of the Fan 2 driver Sets the maximum change per update for Fan 2 Sets the minimum drive value for the Fan 2 driver
LOCK SWL SWL SWL SWL SWL
PAGE Page 37 Page 39 Page 40 Page 40
Page 41 SWL No No No No Page 41 Page 41 Page 42 Page 42
40h
R/W
Fan 2 Setting
00h
No
Page 32
41h
R/W
PWM 2 Divide Fan 2 Configuration1 Fan 2 Configuration 2 Gain 2 Fan 2 Spin Up Configuration Fan 2 Max Step Fan 2 Minimum Drive
01h
No
Page 33
42h
R/W
2Bh
No
Page 33
43h
R/W
28h
SWL
Page 35
45h
R/W
2Ah
SWL
Page 36
46h 47h 48h
R/W R/W R/W
19h 10h 66h (40%)
SWL SWL SWL
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Table 5.1 EMC2303 Register Set (continued) REGISTER NAME Fan 2 Valid TACH Count Fan 2 Drive Fail Band Low Byte Fan 2 Drive Fail Band High Byte TACH 2 Target Low Byte TACH 2 Target High Byte TACH 2 Reading High Byte TACH 2 Reading Low Byte DEFAULT VALUE F5h 00h 00h F8h FFh FFh F8h
ADDR 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh
R/W R/W R/W R/W R/W R/W R R
FUNCTION Holds the tachometer reading that indicates Fan 2 is spinning properly Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive Holds the target tachometer setting low byte for Fan 2 Holds the target tachometer setting high byte for Fan 2 Holds the tachometer reading high byte for Fan 2 Holds the tachometer reading low byte for Fan 2 Fan 3 Control Registers Always displays the most recent fan driver input setting for Fan 3. If the RPM-based Fan Speed Control Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the frequency for Fan 3 Sets configuration values for the RPMbased Fan Speed Control Algorithm for the Fan 3 driver Sets additional configuration values for the Fan 3 driver Holds the gain terms used by the RPMbased Fan Speed Control Algorithm for the Fan 3 driver Sets the configuration values for Spin Up Routine of the Fan 3 driver Sets the maximum change per update for the Fan 3 driver Sets the minimum drive value for the Fan 3 driver Holds the tachometer reading that indicates Fan 3 is spinning properly Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive
LOCK SWL SWL
PAGE Page 40
Page 41 SWL No No No No Page 41 Page 41 Page 42 Page 42
50h
R/W
Fan 3 Setting
00h
No
Page 32
51h
R/W
PWM 3 Divide Fan 3 Configuration 1 Fan 3 Configuration 2 Gain 3 Fan 3 Spin Up Configuration Fan 3 Max Step Fan 3 Minimum Drive Fan 3 Valid TACH Count Fan 3 Drive Fail Band Low Byte Fan 3 Drive Fail Band High Byte
01h
No
Page 33
52h
R/W
2Bh
No
Page 33
53h
R/W
28h
SWL
Page 35
55h
R/W
2Ah
SWL
Page 36
56h 57h 58h 59h 5Ah 5Bh
R/W R/W R/W R/W R/W R/W
19h 10h 66h (40%) F5h 00h 00h
SWL SWL SWL SWL SWL
Page 37 Page 39 Page 40 Page 40
Page 41 SWL
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Table 5.1 EMC2303 Register Set (continued) REGISTER NAME TACH 3 Target Low Byte TACH 3 Target High Byte TACH 3 Reading High Byte TACH 3 Reading Low Byte DEFAULT VALUE F8h FFh FFh F8h
ADDR 5Ch 5Dh 5Eh 5Fh
R/W R/W R/W R R
FUNCTION Holds the target tachometer reading low byte for Fan 3 Holds the target tachometer reading high byte for Fan 3 Holds the tachometer reading high byte for Fan 3 Holds the tachometer reading low byte for Fan 3 Lock Register
LOCK No No No No
PAGE Page 41 Page 41 Page 42 Page 42
EF
R/W
Software Lock
Locks all SWL registers Revision Registers
00h
SWL
Page 43
FCh FDh FEh FFh
R R R R
Product Features Product ID Manufacturer ID Revision
Indicates functions determined upon device power up by external pin states Stores the unique Product ID Stores the Manufacturer ID Revision
00h 35h 5Dh 80h
No No No No
Page 43 Page 44 Page 45 Page 45
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect.
5.1.1
Lock Entries
The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set.
5.2
Configuration Register
Table 5.2 Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1 DR_EXT_ CLK
B0 USE_ EXT_ CLK
DEFAULT
20h
R/W
Configuration
MASK
DIS_TO
WD_EN
-
-
-
40h
The Configuration Register controls the basic functionality of the EMC2303. The bits are described below. The Configuration Register is software locked. Bit 7 - MASK - Blocks the ALERT# pin from being asserted. `0' (default) - The ALERT# pin is unmasked. If any bit in either status register is set, the ALERT# pins will be asserted (unless individually masked via the Mask Register). `1' - The ALERT# pin is masked and will not be asserted.
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Bit 6 - DIS_TO - Disables the SMBus timeout function for the SMBus client (if enabled). `0' - The SMBus timeout function is enabled. `1' (default) - The SMBus timeout function is disabled allowing the device to be fully I2C compliant. Bit 5 - WD_EN - Enables the Watchdog timer to operate in Continuous Mode (see Section 4.8.2). `0' (default) - The Watchdog timer does not operate continuously. It will function upon power up and at no other time. `1' - The Watchdog timer operates continuously as described in Section 4.8. Bit 1 - DR_EXT_CLK - Enables the internal tachometer clock to be driven out on the CLK pin so that multiple devices can be synced to the same source. `0' (default) - The CLK pin acts as a clock input. `1' - The CLK pin acts as a clock output and is a push-pull driver. Bit 0 - USE_EXT_CLK - Enables the EMC2303 to use a clock present on the CLK pin as the tachometer clock. If the DR_EXT_CLK bit is set, then this bit is ignored and the device will use the internal oscillator. `0' (default) - The EMC2303 will use its internal oscillator for all Tachometer measurements. `1' - The EMC2303 will use the oscillator presented on the CLK pin for all Tachometer measurements.
5.3
Fan Status Registers
Table 5.3 Fan Status Registers
ADDR 24h 25h 26h 27h
R/W R-C R-C R-C R-C
REGISTER Fan Status Fan Stall Status Fan Spin Status Fan Drive Fail Status
B7 WATCH -
B6 -
B5 -
B4 -
B3 -
B2 DRIVE_ FAIL FAN3_ STALL FAN3_ SPIN DRIVE_ FAIL3
B1 FAN_ SPIN FAN2_ STALL FAN2_ SPIN DRIVE_ FAIL2
B0 FAN_ STALL FAN1_ STALL FAN1_ SPIN DRIVE_ FAIL1
DEFAULT 00h 00h 00h 00h
The Fan Status registers contain the status bits associated with each fan driver.
5.3.1
Fan Status - 24h
The Fan Status register indicates that one or more of the fan drivers has stalled or failed or that the Watchdog Timer has expired (see Section 4.8). Bit 7 - WATCH - Indicates that the Watchdog Timer has expired. When set, each fan is driven to 100% duty cycle and will remain at 100% duty cycle until they are programmed. This bit is cleared when it is read. Bit 2 - DRIVE_FAIL - Indicates that one or more fan drivers cannot meet the programmed fan speed at maximum PWM duty cycle. This bit is set when any bit in the Fan Drive Fail Status register is set and cleared when all bits in the Fan Drive Fail Status register are cleared. Bit 1 - FAN_SPIN - Indicates that one or more fan drivers cannot spin up. This bit is set when any bit in the Fan Spin Status register is set and cleared when all of the bits in the Fan Spin Status register are cleared.
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Bit 0 - FAN_STALL - Indicates that one or more fan drivers have stalled. This bit is set when any bit in the Fan Stall Status register is set and cleared when all of the bits in the Fan Stall Status register are cleared.
5.3.2
Fan Stall Status - 25h
The Fan Stall Status register indicates which fan driver has detected a stalled condition (see Section 4.4.1). All bits are cleared upon a read if the error condition has been removed. Bit 2 - FAN3_STALL - Indicates that Fan 3 has stalled. Bit 1 - FAN2_STALL - Indicates that Fan 2 has stalled. Bit 0 - FAN1_STALL - Indicates that Fan 1 has stalled.
5.3.3
Fan Spin Status - 26h
The Fan Spin Status register indicates which fan driver has failed to spin-up (see Section 4.6). All bits are cleared upon a read if the error condition has been removed. Bit 2 - FAN3_SPIN - Indicates that Fan 3 has failed to spin up. Bit 1 - FAN2_SPIN - Indicates that Fan 2 has failed to spin up. Bit 0 - FAN1_SPIN - Indicates that Fan 1 has failed to spin up.
5.3.4
Fan Drive Fail Status - 27h
The Fan Drive Fail Status register indicates which fan driver cannot drive to the programmed speed even at 100% duty cycle (see Section 4.4.2 and Section 5.12). All bits are cleared upon a read if the error condition has been removed. Bit 2 - DRIVE_FAIL3 - Indicates that Fan 3 cannot reach its programmed fan speed even at 100% duty cycle. This may be due to an aging fan or invalid programming. Bit 1 - DRIVE_FAIL2 - Indicates that Fan 2 cannot reach its programmed fan speed even at 100% duty cycle. This may be due to an aging fan or invalid programming. Bit 0 - DRIVE_FAIL1 - Indicates that Fan 1 cannot reach its programmed fan speed even at 100% duty cycle. This may be due to an aging fan or invalid programming.
5.4
Fan Interrupt Enable Register
Table 5.4 Fan Interrupt Enable Register
ADDR
R/W
REGISTER Fan Interrupt Enable
B7
B6
B5
B4
B3
B2 FAN3_ INT_EN
B1 FAN2_ INT_EN
B0 FAN1_ INT_EN
DEFAULT
29h
R/W
-
-
-
-
-
00h
The Fan Interrupt Enable controls the masking for each Fan channel. When a channel is enabled, it will cause the ALERT# pin to be asserted when an error condition is detected. Bit 2 - FAN3_INT_EN - Allows Fan 3 to assert the ALERT# pin if an error is detected. Bit 1 - FAN2_INT_EN - Allows Fan 2 to assert the ALERT# pin if an error is detected. Bit 0 - FAN1_INT_EN - Allows Fan 1 to assert the ALERT# pin if an error condition is detected.
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`0' (default) - An error condition on Fan X will not cause the ALERT# pin to be asserted, however the status registers will be updated normally. `1' - An error condition (Stall, Spin Up, Drive Fail) on Fan X will cause the ALERT# pin to be asserted.
5.5
PWM Configuration Registers
Table 5.5 PWM Configuration Registers
ADDR 2Ah 2Bh
R/W R/W R/W
REGISTER PWM Polarity Config PWM Output Config
B7 -
B6 -
B5 -
B4 -
B3 -
B2 POLARITY 3 PWM3_OT
B1 POLARITY 2 PWM2_OT
B0 POLARITY 1 PWM1_OT
DEFAULT 00h 00h
The PWM Config registers control the output type and polarity of all PWM outputs.
5.5.1
PWM Polarity Config - 2Ah
Bit 2 - POLARITY3 - Determines the polarity of PWM 3. Bit 1 - POLARITY2 - Determines the polarity of PWM 2. Bit 0 - POLARITY1 - Determines the polarity of PWM 1. `0' (default) - the Polarity of the PWM driver is normal. A drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100% duty cycle. `1' - The Polarity of the PWM driver is inverted. A drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty cycle.
5.5.2
PWM Output Config - 2Bh
Bit 2 - PWM3_OT - Determines the output type of the of PWM 3 driver. Bit 1 - PWM2_OT - Determines the output type of PWM 2 driver. Bit 0 - PWM1_OT - Determines the output type of the PWM 1 driver. `0' (default) - The PWM 1 output is configured as an open drain output. `1' - The PWM 1 output is configured as a push-pull output.
5.6
PWM Base Frequency Register
Table 5.6 PWM Base Frequency Register
ADDR
R/W
REGISTER PWM Base Frequency
B7
B6
B5 PWM_ BASE 3_1
B4 PWM_ BASE 3_0
B3 PWM_ BASE 2_1
B2 PWM_ BASE 2_0
B1 PWM_ BASE 1_1
B0 PWM_ BASE 1_0
DEFAULT
2Dh
R/W
-
-
00h
The PWM Base Frequency register determines the base frequency that is used with the PWM Divide register to determine the final PWM frequency. Each PWM frequency is set by the base frequency and its respective divide ratio (see Section 5.8).
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Controls the base frequency of PWM drivers 1-3 Bits 5-6 - PWM_BASE3[1:0] - Determines the base frequency of the PWM3 driver. Bits 3-2 - PWM_BASE2[1:0] - Determines the base frequency of the PWM2 driver. Bits 1-0 - PWM_BASE1[1:0] - Determines the base frequency of the PWM1 driver.
Table 5.7 PWM_BASEx[1:0] Bit Decode PWM_BASEX[1:0] 1 0 0 1 1 0 0 1 0 1 BASE FREQUENCY 26.00kHz (default) 19.531kHz 4,882Hz 2,441Hz
5.7
Fan Setting Registers
Table 5.8 Fan Driver Setting Registers
ADDR 30h 40h 50h
R/W R/W R/W R/W
REGISTER Fan 1 Setting Fan 2 Setting Fan 3 Setting
B7 128 128 128
B6 64 64 64
B5 32 32 32
B4 16 16 16
B3 8 8 8
B2 4 4 4
B1 2 2 2
B0 1 1 1
DEFAULT 00h 00h 00h
The Fan Setting register always displays the current setting of the respective fan driver. Reading from any of the registers will report the current fan speed setting of the appropriate fan driver regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. While the RPM-based Fan Speed Control Algorithm is active, the register is read only. Writing to the register will have no effect and the data will not be stored. The contents of the register represent the weighting of each bit in determining the final output voltage. The output drive for a PWM output is given by Equation [1].
VALUE Drive = -------------------- x 100% 255
[1]
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5.8
PWM Divide Registers
Table 5.9 PWM Divide Registers
ADDR 31h 41h 51h
R/W R/W R/W R/W
REGISTER Fan 1 Divide Fan 2 Divide Fan 3 Divide
B7 128 128 128
B6 64 64 64
B5 32 32 32
B4 16 16 16
B3 8 8 8
B2 4 4 4
B1 2 2 2
B0 1 1 1
DEFAULT 01h 01h 01h
The PWM Divide registers determine the final frequency of the respective PWM Fan Driver. Each driver base frequency is divided by the value of the respective PWM Divide Register to determine the final frequency. The duty cycle settings are not affected by these settings, only the final frequency of the PWM driver. A value of 00h will be decoded as 01h.
5.9
Fan Configuration 1 Registers
Table 5.10 Fan Configuration 1 Registers
ADDR 32h 42h 52h
R/W R/W R/W R/W
REGISTER Fan 1 Configuration 1 Fan 2 Configuration 1 Fan 3 Configuration 1
B7 EN_ ALGO1 EN_ ALGO2 EN_ ALGO3
B6
B5
B4
B3
B2
B1
B0
DEFAULT 2Bh 2Bh 2Bh
RANGE1[1:0] RANGE2[1:0] RANGE3[1:0]
EDGES1[1:0] EDGES2[1:0] EDGES3[1:0]
UPDATE1[2:0] UPDATE2[2:0] UPDATE3[2:0]
The Fan Configuration 1 registers control the general operation of the RPM-based Fan Speed Control Algorithm used for the respective Fan Driver. Bit 7 - EN_ALGOx - enables the RPM-based Fan Speed Control Algorithm. `0' - (default) the control circuitry is disabled and the fan driver output is determined by the Fan Driver Setting Register. `1' - the control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register. Bits 6- 5 - RANGEx[1:0] - Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH Target, and TACH reading) as shown in Table 5.11.
Table 5.11 Range Decode RANGEX[1:0] 1 0 0 0 0 1 REPORTED MINIMUM RPM 500 1000 (default) TACH COUNT MULTIPLIER 1 2
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Table 5.11 Range Decode (continued) RANGEX[1:0] 1 1 1 0 0 1 REPORTED MINIMUM RPM 2000 4000 TACH COUNT MULTIPLIER 4 8
Bits 4-3 - EDGESx[1:0] - determines the minimum number of edges that must be detected on the TACHx signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more accurate tachometer measurement, the minimum number of edges measured may be increased. Increasing the number of edges measured with respect to the number of poles of the fan will cause the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to accommodate this shift. The Effective Tach Multiplier shown in Table 5.12 is used as a direct multiplier term that is applied to the Actual RPM to achieve the Reported RPM. It should only be applied if the number of edges measured does not match the number of edges expected based on the number of poles of the fan (which is fixed for any given fan). Contact SMSC for recommended settings when using fans with more or less than 2 poles.
Table 5.12 Minimum Edges for Fan Rotation EDGESX[1:0] 1 0 0 1 1 0 1 0 1 0 MINIMUM TACH EDGES 3 5 7 9 NUMBER OF FAN POLES 1 pole 2 poles (default) 3 poles 4 poles EFFECTIVE TACH MULTIPLIER (BASED ON 2 POLE FANS) 0.5 1 1.5 2
Bit 2-0 - UPDATEx[2:0] - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table 5.13.
Table 5.13 Update Time UPDATEX[2:0] 2 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 UPDATE TIME 100ms 200ms 300ms 400ms (default) 500ms
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Table 5.13 Update Time (continued) UPDATEX[2:0] 2 1 1 1 1 0 1 1 0 1 0 1 UPDATE TIME 800ms 1200ms 1600ms
5.10
Fan Configuration 2 Registers
Table 5.14 Fan Configuration 2 Registers
ADDR 33h 43h 53h
R/W R/W R/W R/W
REGISTER Fan 1 Configuration 2 Fan 2 Configuration 2 Fan 3 Configuration 2
B7 -
B6 EN_ RRC1 EN_ RRC2 EN_ RRC3
B5 GLITCH_ EN1 GLITCH_ EN2 GLITCH_ EN3
B4
B3
B2
B1
B0 -
DEFAULT 28h 28h 28h
DER_OPT1 [1:0] DER_OPT2 [1:0] DER_OPT3 [1:0]
ERR_RNG1[1:0] ERR_RNG2[1:0] ERR_RNG3[1:0]
The Fan Configuration 2 register control the tachometer measurement and advanced features of the RPM-based Fan Speed Control Algorithm. Bit 6 - EN_RRCx - Enables ramp rate control when the corresponding fan driver is operated in the Direct Setting Mode. `0' (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode, the fan setting will instantly transition to the next programmed setting. `1' - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode, the fan drive setting will follow the ramp rate controls as determined by the Fan Step and Update Time settings. The maximum fan drive setting step is capped at the Fan Step setting and is updated based on the Update Time as given by Table 5.13. Bit 5 - GLITCH_ENx - Disables the low pass glitch filter that removes high frequency noise injected on the TACHx pin. `0' - The glitch filter is disabled. `1' (default) - The glitch filter is enabled. Bits 4 - 3 - DER_OPTx[1:0] - Control some of the advanced options that affect the derivative portion of the RPM-based Fan Speed Control Algorithm as shown in Table 5.15.
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Table 5.15 Derivative Options DER_OPTX[1:0] 1 0 0 0 OPERATION No derivative options used Basic derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive Register setting (in addition to proportional and integral terms) (default) Step derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive Register setting and is not capped by the Fan Step Register. Both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term.
0
1
1
0
1
1
Bit 2 - 1 - ERR_RNGx[1:0] - Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on the error; however, these changes are ignored.
Table 5.16 Error Range Options ERR_RNGX[1:0] 1 0 0 1 1 0 0 1 0 1 OPERATION 0 RPM (default) 50 RPM 100 RPM 200 RPM
5.11
Gain Registers
Table 5.17 Gain Registers
ADDR 35h 45h 55h
R/W R/W R/W R/W
REGISTER Gain 1 Register Gain 2 Register Gain 3 Register
B7 -
B6 -
B5
B4
B3
B2
B1
B0
DEFAULT 2Ah 2Ah 2Ah
GAIND1[1:0] GAIND2[1:0] GAIND3[1:0]
GAINI1[1:0] GAINI2[1:0] GAINI3[1:0]
GAINP1[1:0] GAINP2[1:0] GAINP3[1:0]
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The Gain registers store the gain terms used by the proportional and integral portions of each of the RPM-based Fan Speed Control Algorithms. These gain terms are used as the KD, KI, and KP gain terms in a classic PID control solution. Bits 5 - 4 - GAINDX[1:0] - Controls the derivative gain term used by the FSC algorithm as shown in Table 5.18. Bits 3-2 - GAINIX[1:0] - Controls the integral gain term used by the FSC algorithm as shown in Table 5.18. Bits 1-0 - GAINP[1:0] - Controls the proportional gain term used by the FSC algorithm as shown in Table 5.18.
Table 5.18 Gain Decode GAIND OR GAINP OR GAINI [1:0] 1 0 0 1 1 0 0 1 0 1 RESPECTIVE GAIN FACTOR 1x 2x 4x (default) 8x
5.12
Fan Spin Up Configuration Registers
Table 5.19 Fan Spin Up Configuration Registers
ADDR 36h 46h 56h
R/W R/W R/W R/W
REGISTER Fan 1 Spin Up Configuration Fan 2 Spin up Configuration Fan 3 Spin up Configuration
B7
B6
B5 NOKICK1 NOKICK2 NOKICK3
B4
B3
B2
B1
B0
DEFAULT 19h 19h 19h
DRIVE_FAIL_ CNT1 [1:0] DRIVE_FAIL_ CNT2 [1:0] DRIVE_FAIL_ CNT3 [1:0]
SPIN_LVL1[2:0] SPIN_LVL2[2:0] SPIN_LVL3[2:0]
SPINUP_TIME 1 [1:0] SPINUP_TIME 2 [1:0] SPINUP_TIME 3[1:0]
The Fan Spin Up Configuration registers control the settings of Spin Up Routine. The Fan Spin Up Configuration registers are software locked. Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail detection function as shown in Table 5.20. This circuitry determines whether the fan can be driven to the desired tach target.
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Table 5.20 DRIVE_FAIL_CNT[1:0] Bit Decode DRIVE_FAIL_CNTX[1:0] 1 0 0 1 1 0 0 1 0 1 NUMBER OF UPDATE PERIODS Disabled - the Drive Fail detection circuitry is disabled (default) 16 - the Drive Fail detection circuitry will count for 16 update periods 32 - the Drive Fail detection circuitry will count for 32 update periods 64 - the Drive Fail detection circuitry will count for 64 update periods
Bit 5 - NOKICKx - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. `0' (default) - The Spin Up Routine will drive the fan driver to 100% for 1/4 of the programmed spin up time before reverting to the programmed spin level. `1' - The Spin Up Routine will not drive the fan driver to 100%. It will set the drive at the programmed spin level for the entire duration of the programmed spin up time. Bits 4 - 2 - SPIN_LVLx[2:0] - Determines the final drive level that is used by the Spin Up Routine as shown in Table 5.21.
Table 5.21 Spin Level SPIN_LVLX[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 SPIN UP DRIVE LEVEL 30% 35% 40% 45% 50% 55% 60% (default) 65%
Bit 1 -0 - SPINUP_TIMEx[1:0] - determines the maximum Spin Time that the Spin Up Routine will run for (see Section 4.6). If a valid tachometer measurement is not detected before the Spin Time has elapsed, then an interrupt will be generated. When the RPM-based Fan Speed Control Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. The Spin Time is set as shown in Table 5.22.
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Table 5.22 Spin Time SPINUP_TIMEX[1:0] 1 0 0 1 1 0 0 1 0 1 TOTAL SPIN UP TIME 250 ms 500 ms (default) 1 sec 2 sec
5.13
Fan Max Step Registers
Table 5.23 Fan Max Step Registers
ADDR 37h 47h 57h
R/W R/W R/W R/W
REGISTER Fan 1 Max Step Fan 2 Max Step Fan 3 Max Step
B7 -
B6 -
B5 32 32 32
B4 16 16 16
B3 8 8 8
B2 4 4 4
B1 2 2 2
B0 1 1 1
DEFAULT 10h 10h 10h
The Fan Max Step registers, along with the Update Time, control the ramp rate of the fan driver response calculated by the RPM-based Fan Speed Control Algorithm. The value of the register represents the maximum step size each fan driver will take between update times (see Section 5.9). When the FSC algorithm is enabled, Ramp Rate control is automatically used. When the FSC is not active, then Ramp Rate control can be enabled by asserting the EN_RRC bit (see Section 5.10). APPLICATION NOTE: The UPDATE bits and Fan Step Register settings operate independently of the RPM-based Fan Speed Control Algorithm and will always limit the fan drive setting. That is, if the programmed fan drive setting (either as determined by the RPM-based Fan Speed Control Algorithm or by manual settings) exceeds the current fan drive setting by greater than the Fan Step Register setting, the EMC2303 will limit the fan drive change to the value of the Fan Step Register. It will use the Update Time to determine how often to update the drive settings. APPLICATION NOTE: If the Fan Speed Control Algorithm is used, the default settings in the Fan Configuration 2 Register will cause the maximum fan step settings to be ignored. The Fan Max Step registers are software locked.
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5.14
Fan Minimum Drive Registers
Table 5.24 Minimum Fan Drive Registers
ADDR
R/W
REGISTER Fan 1 Minimum Drive Fan 2 Minimum Drive Fan 3 Minimum Drive
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT 66h (40%) 66h (40%) 66h (40%)
38h
R/W
128
64
32
16
8
4
2
1
48h
R/W
128
64
32
16
8
4
2
1
58h
R/W
128
64
32
16
8
4
2
1
The Fan Minimum Drive registers store the minimum drive setting for each RPM-based Fan Speed Control Algorithm. The RPM-based Fan Speed Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target Fan Speed is set at FFh (see Section 5.17). During normal operation, if the fan stops for any reason (including low drive), the RPM-based Fan Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Register to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. The Fan Minimum Drive Registers are software locked.
5.15
Valid TACH Count Registers
Table 5.25 Valid TACH Count Registers
ADDR 39h 49h 59h
R/W R/W R/W R/W
REGISTER Valid TACH Count 1 Valid TACH Count 2 Valid TACH Count 3
B7 4096 4096 4096
B6 2048 2048 2048
B5 1024 1024 1024
B4 512 512 512
B3 256 256 256
B2 128 128 128
B1 64 64 64
B0 32 32 32
DEFAULT F5h F5h F5h
The Valid TACH Count registers store the maximum TACH Reading Register value to indicate that each fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and decide if the device needs to retry. See Equation [2] in Section 5.18 for translating the count to an RPM. If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up Routine. If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. The Valid TACH Count registers are software locked.
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5.16
Fan Drive Fail Band Registers
Table 5.26 Fan Drive Fail Band Registers
ADDR
R/W
REGISTER Fan 1 Drive Fail Band Low Byte Fan 1 Drive Fail Band High Byte Fan 2 Drive Fail Band Low Byte Fan 2 Drive Fall Band High Byte Fan 3 Drive Fail Band Low Byte Fan 3 Drive Fail Band High Byte
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
3Ah
R/W
16
8
4
2
1
-
-
-
00h
3Bh
R/W
4096
2048
1024
512
256
128
64
32
00h
4Ah
R/W
16
8
4
2
1
-
-
-
00h
4Bh
R/W
4096
2048
1024
512
256
128
64
32
00h
5Ah
R/W
16
8
4
2
1
-
-
-
00h
5Bh
R/W
4096
2048
1024
512
256
128
64
32
00h
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed is compared against the target fan speed. These registers are only used when the FSC is active. This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits, then the DRIVE_FAIL status bit will be set and an interrupt generated.
5.17
TACH Target Registers
Table 5.27 TACH Target Registers
ADDR 3Ch 3Dh 4Ch 4Dh
R/W R/W R/W R R/W
REGISTER TACH Target 1 Low Byte TACH Target 1 High Byte TACH Target 2 Low Byte TACH Target 2 High Byte
B7 16 4096 16 4096
B6 8 2048 8 2048
B5 4 1024 4 1024
B4 2 512 2 512
B3 1 256 1 256
B2 128 128
B1 64 64
B0 32 32
DEFAULT F8h FFh F8h FFh
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Table 5.27 TACH Target Registers (continued) ADDR 5Ch 5Dh R/W R R/W REGISTER TACH Target 3 Low Byte TACH Target 3 High Byte B7 16 4096 B6 8 2048 B5 4 1024 B4 2 512 B3 1 256 B2 128 B1 64 B0 32 DEFAULT F8h FFh
The TACH Target Registers hold the target tachometer value that is maintained by the RPM-based Fan Speed Control Algorithm. The value in the TACH Target Registers will always reflect the current TACH Target value. If one of the algorithms is enabled, setting the TACH Target Register to FFh will disable the fan driver (set the fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of FFh) will cause the algorithm to invoke the Spin Up Routine after which it will function normally. The Tach Target is not applied until the high byte is written. Once the high byte is written, the current value of both high and low bytes will be used as the next Tach target.
5.18
TACH Reading Registers
Table 5.28 TACH Reading Registers
ADDR 3Eh 3Fh 4Eh 4Fh 5Eh 5Fh
R/W R R R R R R
REGISTER Fan 1 TACH Fan 1 TACH Low Byte Fan 2 TACH Fan 2 TACH Low Byte Fan 3 TACH Fan 3 TACH Low Byte
B7 4096 16 4096 16 4096 16
B6 2048 8 2048 8 2048 8
B5 1024 4 1024 4 1024 4
B4 512 2 512 2 512 2
B3 256 1 256 1 256 1
B2 128 128 128 -
B1 64 64 64 -
B0 32 32 32 -
DEFAULT FFh F8h FFh F8h FFh F8h
The TACH Reading Registers' contents describe the current tachometer reading for each of the fans. By default, the data represents the fan speed as the number of 32kHz clock periods that occur for a single revolution of the fan. Equation [2] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation [3] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768kHz. These equations are solved and tabulated for ease of use in AN17.4 RPM to TACH Counts Conversion. Whenever the high byte register is read, the corresponding low byte data will be loaded to internal shadow registers so that when the low byte is read, the data will always coincide with the previously read high byte.
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where: poles = number of poles of the fan (typically 2) 1(n - 1) RPM = ------------------- x --------------------------------- x f TACH x 60 ( poles ) 1COUNT x ---m fTACH = the tachometer measurement frequency (typically 32.768kHz) n = number of edges measured (typically 5 for a 2 pole fan) m = the multiplier defined by the RANGE bits [3] COUNT = TACH Reading Register value (in decimal) [2]
3,932,160 x m RPM = ------------------------------------COUNT
5.19
Software Lock Register
Table 5.29 Software Lock Register
ADDR EFh
R/W R/W
REGISTER Software Lock
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 -
B0 LOCK
DEFAULT 00h
The Software Lock Register controls the software locking of critical registers. This register is software locked. Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked registers become read only and cannot be updated. `0' (default) - all SWL registers can be updated normally. `1' - all SWL registers cannot be updated and a hard-reset is required to unlock them.
5.20
Product Features Register
Table 5.30 Product Features Register
ADDRESS FCh
R/W R
REGISTER Product Features
B7 -
B6 -
B5
B4 ADR[2:0]
B3
B2
B1
B0
DEFAULT 00h
FAN_SPD [2:0]
The Product Features register shows those functions that are enabled by external pin states. Bits 5-3 - ADR[2:0] - Indicates the selected SMBus address as determined by the ADDR_SEL pin.
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Table 5.31 ADDR_SEL Pin Configuration ADR[2:0] SLAVE ADDRESS 2 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0101_110(r/w) 0101_111(r/w) 0101_100(r/w) 0101_101(r/w) 1001_100(r/w) 1001_101(r/w)
Bits 2-0 - FAN_SPD[2:0] - Indicates the selected fan speed if the CLK pin pull-up decode is enabled via the ADDR_SEL pin.
Table 5.32 FAN_SPD Pin Configuration FAN_SPD [2:0] FAN SPEED 2 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0% Drive 30% Drive 50% Drive 75% Drive 100% Drive
5.21
Product ID Register
Table 5.33 Product ID Register
ADDR FDh
R/W R
REGISTER Product ID
B7 0
B6 0
B5 1
B4 1
B3 0
B2 1
B1 0
B0 1
DEFAULT 35h
The Product ID Register contains a unique 8-bit word that identifies the product.
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5.22
Manufacturer ID Register
Table 5.34 Manufacturer ID Register
ADDR FEh
R/W R
REGISTER Manufacturer ID
B7 0
B6 1
B5 0
B4 1
B3 1
B2 1
B1 0
B0 1
DEFAULT 5Dh
The Manufacturer ID Register contains an 8-bit word that identifies SMSC.
5.23
Revision Register
Table 5.35 Revision Register
ADDR FFh
R/W R
REGISTER Revision
B7 1
B6 0
B5 0
B4 0
B3 0
B2 0
B1 0
B0 0
DEFAULT 80h
The Revision Register contains an 8-bit word that identifies the die revision.
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Chapter 6 Typical Operating Curves
The following Typical Operating Curves are included. Supply Current vs. Temperature Supply Current vs. Supply Voltage Fan TACH Accuracy vs. Temperature Fan TACH Accuracy vs. Supply Voltage PWM output frequency vs. Supply Voltage PWM output frequency vs. Temperature FSC Operation
Supply Current vs. Ambient Temperature 600 550
Supply Current (uA) Supply Current (uA)
Supply Current vs. Supply Voltage 600 550
Supply Current (uA) Supply Current (uA)
500 450 400 350 300 -50
500 450 400 350 300 2.95
3.05
3.15
3.25
3.35
3.45
3.55
3.65
0
50
Ambient Temperature (C) Temperature (C)
100
150
Supply Voltage Supply Voltage (V) (V)
Tachometer Measurement Accuracy vs. Ambient Temperature 1
Tachometer Measurement Accuracy vs. Supply Voltage 1
Tach Measurement Accuracy (%) Tach Measurement Accuracy (%
Tach Measurement Accuracy (% Tach Measurement Accuracy (%)
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 0 50 100 150
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
Temperautre (C) Ambient Temperature (C)
Supply Voltage (V)
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PWM Frequency vs. Ambient Temperature V DD = 3.3V, Base Frequncy = 26Khz 27000 26800 26600
PWM Frequency (Hz)
PWM Frequency vs. Supply Voltage TA = 25C, Base Frequncy = 26Khz 27000 26800 26600
PWM Frequency (Hz)
26400 26200 26000 25800 25600 25400 25200 25000 -50 0 50 100 150
26400 26200 26000 25800 25600 25400 25200 25000 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
T emp er at ur e (C) Ambient Temperature( C )
Supply Voltage (V)
FSC Algorithm Spin Up Routine Spin Time = 1.0s; Spin Level = 55%; Updated Time = 200ms; RPM Target from 0 RPM -> 8000 RPM @ time t = 0
FSC Algorithm Spin Up Routine - NoKick Spin Time = 1.0s; Spin Level = 50%; UpdateTime = 200ms; RPM Target from 0 RPM -> 8000 RPM @ time t = 0
PWM Output
PWM Output
10x Zoom on PWM Output
10x Zoom on PWM Output
t=0
Duty Cycle Measured = 53.8%
t=0
Duty Cycle Measured = 50%
FSC Algorithm PWM Ramping Update Time = 200ms; Max Step = 16 PWM counts RPM Target from 0 RPM -> 8000 RPM @ time t = 0
PWM Output
10x Zoom on PWM Output
Spin Up Routine Ends - begins normal operation Update Time ends, PWM duty cycle changed
Duty Cycle Measured
Update Time ends, PWM duty cycle changed
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Chapter 7 Package Drawing
7.1 EMC2303 Package Information
Figure 7.1 Package Drawing - 12-Pin QFN 4mm x 4mm
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Figure 7.2 Package Dimensions - 12-Pin QFN 4mm x 4mm
Figure 7.3 PCB Footprint - 12-Pin QFN 4mm x 4mm
Revision 1.1 (10-12-09) 50 SMSC EMC2303
DATASHEET
Multiple RPM-Based PWM Fan Controller Datasheet
7.2
Package Markings
TOP
0.41 LINE: 1 - SMSC Logo without circled (R) symbol LINE: 2 - Device Number LINE: 3 - Last 7 digits of Lot Number LINE: 4 - Revision and Country Code (RCC) 2303 -1 123456a RCC e3
PIN 1
3x 0.56
PB-FREE/GREEN SYMBOL (Matte Sn) LINES 1 to 3: CENTER HORIZONTAL ALIGNMENT LINE 4: LEFT HORIZONTAL ALIGNMENT
BOTTOM BOTTOM MARKING NOT ALLOWED
Figure 7.4 EMC2303 Package Markings
SMSC EMC2303
51
Revision 1.1 (10-12-09)
DATASHEET

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